1. Field of the Invention
The present invention relates to packet switches, and more particularly to an arbitrarily large packet switch.
2. Description of the Prior Art
The internal components of a packet switch often operate several times faster than the rate at which the packet switch receives or transmits packets. This speed of operation is necessary to enable the packet switch to route different packets, simultaneously received at multiple inputs, to the same output. However, such a high speed of operation requires that the packet switch be implemented on a single integrated circuit chip or a single circuit card, and thus, the number of inputs and outputs which a packet switch can comprise is limited by the number of inputs and outputs which can be placed on a circuit chip or a circuit card. One packet switch which overcomes the problem in some regard is disclosed in U.S. Pat. No. 4,577,308, issued to Larson et al. on Mar. 18, 1986. In this packet switch, several outputs are multiplexed by an on-chip multiplexer, and the multiplexed output signal is sent off the chip by means of a single output lead. Similarly, a multiplexed input stream is received at a single input pin of the chip, and an on chip demultiplexer demultiplexes the signal and supplies the separated input signals to separate inputs of the packet switch. Although this overcomes some of the difficulties of prior art devices, it requires on-chip multiplexing/demultiplexing, and, therefore, the allowable size of the packet switch is still limited. The problem that remains is to provide a packet switch which can be modularly grown as large as an expanding network may require.